Due - Sunday, November 23, 2025
This is a group project of 2 or 3 students per group. The groups can be found in the document Lab4_Groups.docx.
You really were not fond of the Analog Circuit Simulator ANASIM. To your surprise and to the surprise of the company executives, the product sold successfully. To reward your good work the company has promoted you to a dual role of senior software engineer/project manager. You now have to come up with ANASIM version 2.0, and this is your opportunity to improve this product as well as the processes related to its completion.
There are three areas that you feel need improvement to this product: the user interface, the capabilities of the simulator, and the software development process at your company in general. The user interface will determine how the user enters circuit information into the simulator as well as how the output information will be presented. The capabilities of the simulator have to be expanded for complex circuit configurations. The software development process could be improved in this project and emulated in other projects.
Version 1.0 required the circuit components to be hard-coded inside of the code itself. This is clearly unacceptable. You have identified three ways in which a customer could enter circuit connectivity.
Having the program obtain circuit information through a graphical interface is very user friendly.
TASK 1: What type of GUI would you use, with which computer languages? (1 mark)
TASK 2: Is this type of user interaction (GUI) suitable for complex circuits? (1 mark)
Having the program obtain circuit information through a netlist is not very user friendly. A netlist for a series/parallel circuit
might look as follows:
1 0 V1 1
1 0 R1 100
1 0 R2 100
1 2 R3 100
2 0 C1 0.000001
The above describes the following circuit:
TASK 3: Explain what advantage a netlist has over a graphical user interface? (1 mark)
TASK 4: Could both GUI and netlist formats be used? How would this work? (1 mark)
The circuit simulator so far can only simulate components in series. You need to be able to simulate components in parallel as well. To do so, you need to define "nodes" and "branches" in your circuit. A "branch" is a set of components connected in series. A "node" is a point where more than two components are connected.
An algorithm for series/parallel circuits might work as follows. If we have the voltage drop across a branch, we already know how to determine the current with our cost function for the voltage. If we have currents going into and out of a node, we might have to develop a cost function for the current. These cost functions have to somehow work together to provide a solution for all voltages and currents in the circuit.
Since you have been given much more power over the development life cycle, you now have the authority to modify the delivery schedule. You decide that an iterative approach is better.
TASK 5: Since ANASIM 2.0 has introduced some new capabilities, list the project deliverables available for each iterative cycle. (1 mark)
To improve the software development process, you must tackle the following issues:
TASK 6: Who really defines the scope of this project and why? (1 mark)
TASK 7: Can you suggest a systematic way of identifying customer needs? (1 mark)
TASK 8: Identify all components of this project which could be reused in similar projects. (1 mark)
TASK 9: Can you come up with a general product support strategy for maintenance and enhancements for future releases, that could
be used for other projects? (1 mark)
TASK 10: What type of documentation would you use internally, versus documentation for the customer? (1 mark)
Note that this lab partially fulfills one of the
Canadian Engineering Accreditation Board
graduate attributes that our engineering graduates should have:
- Design (DE.5).
The attribute is assessed here.
All questions and tasks have been embedded within the assignment. Below is the marking rubric:
| Does not meet expectations | Satisfactory | Good | Exceeds Expectations | |
|---|---|---|---|---|
User Interface Tasks 1-4 (4 marks) | Does not meet requirements | Meets the most important requirements | Meets all requirements with minor errors | Meets all requirements with no errors |
The Software Development Process Tasks 5-10 (6 marks) | Does not meet requirements | Meets the most important requirements | Meets all requirements with minor errors | Meets all requirements with no errors |
Please email all documents to: miguel.watler@senecapolytechnic.ca
You will be docked 10% if your lab is submitted 1-2 days late.
You will be docked 20% if your lab is submitted 3-4 days late.
You will be docked 30% if your lab is submitted 5-6 days late.
You will be docked 40% if your lab is submitted 7-8 days late.
You will be docked 50% if your lab is submitted 9-10 days late.
You will be docked 100% if your lab is submitted over 10 days late.